The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Mar. 01, 2012
Applicants:

Hamed Fatemi, Eindhoven, NL;

Ajay Kapoor, Eindhoven, NL;

Jose Pineda DE Gyvez, Eindhoven, NL;

Inventors:

Hamed Fatemi, Eindhoven, NL;

Ajay Kapoor, Eindhoven, NL;

Jose Pineda de Gyvez, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 15/00 (2006.01); G06F 9/38 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/5094 (2013.01);
Abstract

Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a schedule allocates the data and schedule to a plurality of computational units. The scheduler also modifies voltage and frequency settings of the processing architecture to optimize power consumption and throughput of the system. The computational units include control units and execute units. The control units receive and decode the instructions and send the decoded instructions to execute units. The execute units then execute the instructions according to relevant software.


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