The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jan. 14, 2013
Applicant:

Liming Xiu, Plano, TX (US);

Inventor:

Liming Xiu, Plano, TX (US);

Assignee:

Liming Xiu, Plano, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); G06F 1/08 (2006.01); H03K 23/66 (2006.01); H03K 23/68 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 23/667 (2013.01); H03K 23/68 (2013.01);
Abstract

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (f) and the destination frequency (f). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.


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