The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jan. 29, 2014
Applicant:

Julian Jenkins, Kurraba Point, AU;

Inventor:

Julian Jenkins, Kurraba Point, AU;

Assignee:

Perceptia Devices Australia Pty Ltd, Kurraba Point, NSW, AU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/16 (2006.01); H03L 7/197 (2006.01); H03L 7/087 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03L 7/087 (2013.01); H03L 7/16 (2013.01); H03L 2207/50 (2013.01);
Abstract

A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.


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