The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Nov. 21, 2013
Applicant:
Seiko Instruments Inc., Chiba, JP;
Inventors:
Takeshi Koyama, Chiba, JP;
Yoshitsugu Hirose, Chiba, JP;
Assignee:
Seiko Instruments Inc., , JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 29/76 (2006.01); H01L 27/02 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H01L 29/41758 (2013.01); H01L 29/4238 (2013.01); H01L 29/0692 (2013.01); H01L 23/4824 (2013.01); H01L 27/0274 (2013.01);
Abstract
Provided is a semiconductor device having high ESD tolerance. A first via () is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via () is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.