The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Oct. 24, 2013
Seiko Instruments Inc., Chiba, JP;
Takeshi Koyama, Chiba, JP;
Yoshitsugu Hirose, Chiba, JP;
Seiko Instruments Inc., , JP;
Abstract
Provided is a semiconductor device having high ESD tolerance. A first via () is used for electrically connecting a pad () to a drain of an NMOS transistor of an ESD protective circuit. The first vias () are formed under the pad () only on one side of a rectangular ring-shaped intermediate metal film () and on another side thereof opposed to the one side. In other words, all the first vias () for establishing an electrical connection to the drains are present substantially directly under the pad (). Consequently, a surge current caused by ESD and applied to the pad () is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.