The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9006801 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 14, 2015

Filed:

Jan. 25, 2011
Applicants:

Christian Lavoie, Ossining, NY (US);

Zhengwen LI, Danbury, CT (US);

Ahmet S. Ozcan, Pleasantville, NY (US);

Filippos Papadatos, Wappingers Falls, NY (US);

Chengwen Pei, Danbury, CT (US);

Jian Yu, Danbury, CT (US);

Inventors:

Christian Lavoie, Ossining, NY (US);

Zhengwen Li, Danbury, CT (US);

Ahmet S. Ozcan, Pleasantville, NY (US);

Filippos Papadatos, Wappingers Falls, NY (US);

Chengwen Pei, Danbury, CT (US);

Jian Yu, Danbury, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/6659 (2013.01); H01L 29/7843 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01);
Abstract

A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.


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