The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
May. 18, 2011
Applicants:
Wei-yu Yeh, Tainan, TW;
Pei-wen Ko, Zhubei, TW;
Chih-hsuan Sun, Kaohsiung, TW;
Hsueh-hung Fu, Hsinchu, TW;
Inventors:
Wei-Yu Yeh, Tainan, TW;
Pei-Wen Ko, Zhubei, TW;
Chih-Hsuan Sun, Kaohsiung, TW;
Hsueh-Hung Fu, Hsinchu, TW;
Assignee:
TSMC Solid State Lighting Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/64 (2010.01); H05K 1/02 (2006.01); H01L 33/62 (2010.01); H05K 1/05 (2006.01);
U.S. Cl.
CPC ...
H01L 33/641 (2013.01); H05K 1/0203 (2013.01); H01L 33/62 (2013.01); H01L 2933/0075 (2013.01); H05K 2201/10106 (2013.01); H05K 1/0206 (2013.01); H05K 1/05 (2013.01); H05K 2201/10969 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A light emitting diode (LED) carrier assembly includes an LED die mounted on a silicon submount, a middle layer that is thermally conductive and electrically isolating disposed below the silicon submount, and a printed circuit board (PCB) disposed below the middle layer. The middle layer is bonded with the silicon submount and the PCB.