The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Sep. 11, 2009
Applicants:
Ananda H. Kumar, Fremont, CA (US);
Ashish Asthana, Fremont, CA (US);
Farooq Quadri, San Ramon, CA (US);
Inventors:
Ananda H. Kumar, Fremont, CA (US);
Ashish Asthana, Fremont, CA (US);
Farooq Quadri, San Ramon, CA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G01R 1/04 (2006.01); H05K 3/40 (2006.01); G01R 3/00 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
G01R 1/0491 (2013.01); G01R 3/00 (2013.01); H05K 1/111 (2013.01); H05K 3/4007 (2013.01); H05K 3/4629 (2013.01); H05K 2201/0367 (2013.01); H05K 2203/308 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15312 (2013.01); H01L 2924/0002 (2013.01);
Abstract
This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices.