The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Jan. 08, 2014
Applicants:

Chetan Verma, Noida, IN;

Kushagra Khorwal, Ghaziabad, IN;

Amit Roy, Noida, IN;

Rounak Roy, Noida, IN;

Vijay Tayal, Noida, IN;

Inventors:

Chetan Verma, Noida, IN;

Kushagra Khorwal, Ghaziabad, IN;

Amit Roy, Noida, IN;

Rounak Roy, Noida, IN;

Vijay Tayal, Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01);
Abstract

A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.


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