The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Mar. 13, 2013
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Avijit Dutta, Tigard, OR (US);

Krishnan Anandh, San Jose, CA (US);

Steven Danz, Tigard, OR (US);

Neil Tuttle, Beaverton, OR (US);

Ryan Morse, Beaverton, OR (US);

Haneef Mohammed, Beaverton, OR (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01);
Abstract

Techniques for reducing post-routing delay variance are described herein. In an example embodiment, an initial netlist includes multiple instances that represent digital components of an electronic design. An base signature is assigned to each instance in the initial netlist, where the base signature is based on two or more design or connectivity attributes of the instance. The base signatures are then used to generate an initial instance ordering of the instances in the initial netlist. A subsequent netlist, different from the initial netlist but representing the same electronic design, is received. Base signatures are assigned to the instances on the subsequent netlist and a subsequent instance ordering is generated. The subsequent instance ordering preserves the same order as the initial instance ordering for those instances that are included in both the initial netlist and the subsequent netlist. In this manner, any later netlist-based processing (e.g., such as packing, placement, and routing) is shielded from the negative re-design effects caused by the subsequent changes to the initial netlist and, consequently, the post-routing timing delay variance of the electronic design is reduced.


Find Patent Forward Citations

Loading…