The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Jan. 30, 2009
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Active-Semi, Inc., , VG;
Abstract
A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.