The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Mar. 15, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Naoto Oshiyama, Tokyo, JP;

Ryo Yamaki, Kanagawa, JP;

Kenta Yasufuku, Kanagawa, JP;

Naoaki Kokubun, Kanagawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); H03M 13/29 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G06F 11/10 (2013.01); G06F 11/1048 (2013.01); H03M 13/1515 (2013.01); H03M 13/152 (2013.01); H03M 13/1525 (2013.01); H03M 13/154 (2013.01); H03M 13/1545 (2013.01); H03M 13/2906 (2013.01); H03M 13/2927 (2013.01); H03M 13/6502 (2013.01); H03M 13/6561 (2013.01);
Abstract

According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.


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