The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Nov. 11, 2011
Muralidhar Ravuri, Sunnyvale, CA (US);
Muralidhar Ravuri, Sunnyvale, CA (US);
Other;
Abstract
Stable Parallel Loop (SPL) systems and exemplary embodiments are described with reference to both software and hardware platforms. A SPL network includes an input surface, internal nodes, connections that selectively link internal nodes, and an output surface. Signals from the environment are received on the input surface. The received signals excite internal nodes of the SPL network. The internal nodes exhibit their own dynamic behavior. As a result of the interconnected network structure and operational characteristics of each node, dynamic loops are formed among certain internal nodes. A dynamic loop is formed when all of internal nodes within an interconnected loop are active. Output from the SPL network is generated based on the dynamic loops that are formed. Tools to develop and implement a SPL network are presented.