The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Apr. 12, 2012
Applicant:
Jong-ho Jung, Gyeonggi-do, KR;
Inventor:
Jong-Ho Jung, Gyeonggi-do, KR;
Assignee:
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 8/00 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 7/1066 (2013.01); G11C 7/222 (2013.01);
Abstract
A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.