The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Feb. 26, 2013
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventor:

Kwang Ho Baek, Icheon-si, KR;

Assignee:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0466 (2013.01); G11C 11/5635 (2013.01); G11C 16/14 (2013.01); G11C 16/3445 (2013.01);
Abstract

A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop.


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