The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Dec. 16, 2011
Applicants:

Ming-dou Ker, Hsinchu, TW;

Cheng-cheng Yen, Hsinchu, TW;

Tung-yang Chen, New Taipei, TW;

Ching-ling Tsai, Tainan, TW;

Shih-fan Chen, Tainan, TW;

Inventors:

Ming-Dou Ker, Hsinchu, TW;

Cheng-Cheng Yen, Hsinchu, TW;

Tung-Yang Chen, New Taipei, TW;

Ching-Ling Tsai, Tainan, TW;

Shih-Fan Chen, Tainan, TW;

Assignees:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H03M 1/36 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/361 (2013.01); G01R 19/0053 (2013.01);
Abstract

A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.


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