The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Jul. 17, 2013
Semtech Corporation, Camarillo, CA (US);
Sandeep Louis D'Souza, Redondo Beach, CA (US);
Krishna Shivaram, Torrance, CA (US);
Craig Allison Hornbuckle, Rolling Hills Estates, CA (US);
Semtech Corporation, Camarillo, CA (US);
Abstract
Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.