The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Feb. 24, 2012
Applicants:

Jinsoup Joung, Seongnam-si, KR;

Joohyeong Lee, Seoul, KR;

Jongho Lim, Seoul, KR;

Seungkeun Yook, Seoul, KR;

Ji Hye Shin, Seoul, KR;

Inventors:

Jinsoup Joung, Seongnam-si, KR;

Joohyeong Lee, Seoul, KR;

Jongho Lim, Seoul, KR;

Seungkeun Yook, Seoul, KR;

Ji Hye Shin, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/47 (2006.01); H03M 13/23 (2006.01); H03M 13/29 (2006.01);
U.S. Cl.
CPC ...
H03M 13/47 (2013.01); H03M 13/235 (2013.01); H03M 13/2903 (2013.01); H03M 13/2957 (2013.01); H03M 13/2993 (2013.01); H03M 13/6575 (2013.01);
Abstract

A turbo encoder apparatus includes: a first element encoder for receiving an input of a bitstream of the data, encoding the input of the bitstream of the data, and generating a first output bitstream in an unit of plural bits; an internal interleaver for generating an interleaved input bitstream from the bitstream of the data; a second element encoder for receiving an input of the interleaved input bitstream in the unit of plural bits, encoding the input of the interleaved input bitstream, and generating a second output bitstream in an unit of plural bits; a trellis-termination-encoder for generating bits for trellis terminations of the first element encoder and the second element encoder; and a bitstream assembler for receiving the first output bitstream, the second output bitstream, and the bits for the trellis terminations and generating an input bitstream for a rate matching.


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