The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Mar. 15, 2013
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Luca Romano, Milan, IT;

Alessandro Venca, Tortona, IT;

Stefano Dal Toso, Montegalda, IT;

Antonio Milani, Marzano, IT;

Brian Brunn, Bee Cave, TX (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/08 (2006.01); H03L 7/07 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03L 7/08 (2013.01); H03L 7/07 (2013.01); H03L 7/0805 (2013.01); H03L 7/0816 (2013.01);
Abstract

In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.


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