The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Aug. 05, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Frank Huebinger, Dresden, DE;

Steffen Rothenhaeusser, Dresden, DE;

Kerstin Kaemmer, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 21/28 (2006.01); H01L 27/02 (2006.01); H01L 21/283 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 27/0207 (2013.01); H01L 29/6659 (2013.01); H01L 21/283 (2013.01); H01L 27/088 (2013.01);
Abstract

A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.


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