The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8999848 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 07, 2015

Filed:

Nov. 16, 2012
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Ki Lyoung Lee, Seoul, KR;

Cheol Kyu Bok, Icheon, KR;

Won Kyu Kim, Icheon, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/302 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/48 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4846 (2013.01); H01L 21/28132 (2013.01); H01L 2924/0002 (2013.01); H01L 27/11531 (2013.01);
Abstract

A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.


Find Patent Forward Citations

Lee, Ki. (2015). Method for forming fine pattern of semiconductor device using double spacer patterning technology (U.S. Patent No. 8999848). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8999848

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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