The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

May. 29, 2013
Applicant:

AU Optronics Corp., Hsin-Chu, TW;

Inventors:

Ssu-Hui Lu, Hsin-Chu, TW;

Ming-Hsien Lee, Hsin-Chu, TW;

Assignee:

AU Optronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/30 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3003 (2013.01); H01L 27/1248 (2013.01); H01L 27/127 (2013.01);
Abstract

A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.


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