The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Mar. 14, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventor:

Hiromitsu Komai, Kamakura, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 3/06 (2006.01); G06F 13/38 (2006.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0646 (2013.01); G06F 13/38 (2013.01); G11C 16/00 (2013.01);
Abstract

According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.


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