The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Dec. 10, 2012
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Kwang-Hyun Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/18 (2006.01); G11C 7/12 (2006.01); G11C 29/12 (2006.01); G11C 11/41 (2006.01); G11C 29/26 (2006.01);
U.S. Cl.
CPC ...
G11C 29/18 (2013.01); G11C 7/12 (2013.01); G11C 11/41 (2013.01); G11C 29/1201 (2013.01); G11C 2029/2602 (2013.01);
Abstract

Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode.


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