The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Mar. 12, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Huu N. Dinh, Cedar Park, TX (US);

Robert S. Horton, Colchester, VT (US);

Bill N. On, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03K 5/159 (2006.01);
U.S. Cl.
CPC ...
H03K 5/159 (2013.01);
Abstract

A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.


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