Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter

Abstract

A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.