The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Dec. 13, 2012
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Renaldi Winoto, Danville, CA (US);

David M. Signoff, Mountain View, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/00 (2006.01); G01R 17/00 (2006.01); G06G 7/163 (2006.01); H03D 7/14 (2006.01); G01R 17/16 (2006.01); G06G 7/16 (2006.01);
U.S. Cl.
CPC ...
G06G 7/163 (2013.01); H03D 7/1441 (2013.01); G01R 17/16 (2013.01); G06G 7/16 (2013.01); H03D 7/1458 (2013.01); H03D 7/1466 (2013.01); H03D 2200/0043 (2013.01);
Abstract

A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance.


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