The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Apr. 19, 2013
Applicant:

Jtekt Corporation, Osaka-shi, Osaka, JP;

Inventor:

Nobuhiro Uchida, Yamatotakada, JP;

Assignee:

JTEKT Corporation, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H02P 6/08 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49568 (2013.01); H02P 6/085 (2013.01); H05K 1/186 (2013.01); H05K 1/0209 (2013.01); H05K 3/4617 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A motor control multilayer printed wiring board includes: a multilayer printed wiring board having a plurality of laminated conductor layers; an upper-row FET connected to the conductor layers and configured to control a motor; a lower-row FET connected to the conductor layers and arranged at a location at which the lower-row FET overlaps with the upper-row FET in a laminated direction in which the conductor layers are laminated, the lower-row FET being configured to control the motor; and a heat dissipation mechanism arranged on the multilayer printed wiring board and arranged at a location at which the heat dissipation mechanism overlaps with at least one of the upper-row FET and the lower-row FET in the laminated direction.


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