The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Apr. 17, 2013
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventors:

Marc Strasser, Unterhaching, DE;

Karl-Heinz Gebhardt, Dresden, DE;

Andreas Meiser, Sauerlach, DE;

Till Schloesser, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01); H01L 29/7823 (2013.01);
Abstract

A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer.


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