The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Feb. 07, 2014
Applicant:

Volterra Semiconductor Corporation, Fremont, CA (US);

Inventors:

Budong You, Fremont, CA (US);

Marco A. Zuniga, Palo Alto, CA (US);

Assignee:

Volterra Semiconductor LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/732 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/26586 (2013.01); H01L 21/823814 (2013.01); H01L 21/823857 (2013.01); H01L 21/8249 (2013.01); H01L 27/0623 (2013.01); H01L 27/0922 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01); H01L 29/7322 (2013.01); H01L 29/7816 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01);
Abstract

A transistor structure includes a p-type substrate, an n-well implanted in the substrate, a p-doped p-body implanted in the n-well, first and second transistors, an input line, and an output line. The first transistor includes a first gate, a first source, and a first drain, and the second transistor includes a second gate, a second source, and a second drain. The first source includes a first p+ region and a first n+ region, and the first drain includes a second n+ region. The second source includes a third n+ region and a second p+ region, and the second drain includes a third p+ region. The input line connects the first gate and the second gate, and the output line connects the second n+ region and the third p+ region.


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