The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Oct. 22, 2009
Applicant:
Dusan Golubovic, Leuven, BE;
Inventor:
Dusan Golubovic, Leuven, BE;
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 29/4234 (2013.01); H01L 29/495 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
The invention relates to a multi-transistor, e.g. a two-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor. In one embodiment, the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. a two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps. Such a multi-transistor, e.g. a two-transistor memory cell according to invention, provides an improved reliability.