The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

May. 24, 2011
Applicants:

Hye-young Ryu, Seoul, KR;

Woo-geun Lee, Yongin-si, KR;

Young-joo Choi, Yongin-si, KR;

Kyoung-jae Chung, Seoul, KR;

Jin-won Lee, Cheonan-si, KR;

Seung-ha Choi, Suwon-si, KR;

Hee-jun Byeon, Suwon-si, KR;

Pil-sang Yun, Seoul, KR;

Inventors:

Hye-Young Ryu, Seoul, KR;

Woo-Geun Lee, Yongin-si, KR;

Young-Joo Choi, Yongin-si, KR;

Kyoung-Jae Chung, Seoul, KR;

Jin-Won Lee, Cheonan-si, KR;

Seung-Ha Choi, Suwon-si, KR;

Hee-Jun Byeon, Suwon-si, KR;

Pil-Sang Yun, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 29/10 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1214 (2013.01); H01L 27/1225 (2013.01);
Abstract

A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.


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