The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Jul. 29, 2011
Applicants:

Dongwoo Suh, Daejeon, KR;

Sung Bock Kim, Daejeon, KR;

Hojun Ryu, Seoul, KR;

Inventors:

Dongwoo Suh, Daejeon, KR;

Sung Bock Kim, Daejeon, KR;

Hojun Ryu, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 29/068 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 21/02381 (2013.01); H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/02639 (2013.01); H01L 21/02645 (2013.01); H01L 21/02653 (2013.01); Y10S 977/762 (2013.01);
Abstract

Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.


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