The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Feb. 21, 2012
Applicants:

Takeshi Suzuki, Osaka, JP;

Koichi Hirano, Osaka, JP;

Shinobu Masuda, Osaka, JP;

Inventors:

Takeshi Suzuki, Osaka, JP;

Koichi Hirano, Osaka, JP;

Shinobu Masuda, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 23/544 (2006.01); H01L 21/027 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66765 (2013.01); H01L 23/544 (2013.01); H01L 2227/323 (2013.01); H01L 2251/5338 (2013.01); H01L 29/78669 (2013.01); H01L 29/78678 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 27/3262 (2013.01); H01L 21/0274 (2013.01); H01L 29/78603 (2013.01); H01L 29/7869 (2013.01); H01L 2924/0002 (2013.01);
Abstract

There is provided a method for manufacturing a flexible semiconductor device. The method of the flexible semiconductor device according to the present invention comprises the steps of: (i) forming an insulating layer on one of principal surfaces of a metal foil; (ii) forming a semiconductor layer on the insulating layer, and then forming source and drain electrodes so that the source and drain electrodes contact with the semiconductor layer; (iii) forming a flexible film layer so that the flexible film layer covers the semiconductor layer and the source and drain electrodes; (iv) forming vias in the flexible film layer, and thereby a semiconductor device precursor is provided; and (v) subjecting the metal foil to a processing treatment, and thereby forming a gate electrode from the metal foil, wherein, in the step (v) of the processing treatment of the metal foil, the gate electrode is formed in a predetermined position by using at least one of the vias of the semiconductor device precursor as an alignment marker.


Find Patent Forward Citations

Loading…