The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Aug. 28, 2013
Applicant:

Hamamatsu Photonics K.k., Hamamatsu-shi, Shizuoka, JP;

Inventors:

Hiroshi Oguri, Hamamatsu, JP;

Yoshitaka Ishikawa, Hamamatsu, JP;

Akira Sakamoto, Hamamatsu, JP;

Tomoya Taguchi, Hamamatsu, JP;

Yoshimaro Fujii, Hamamatsu, JP;

Assignee:

Hamamatsu Photonics K.K., Hamamatsu-shi, Shizuoka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/0232 (2014.01); H01L 31/0224 (2006.01); H01L 31/0352 (2006.01); H01L 31/103 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/02327 (2013.01); H01L 31/022408 (2013.01); H01L 31/0352 (2013.01); H01L 31/03529 (2013.01); H01L 31/103 (2013.01); H01L 31/18 (2013.01);
Abstract

A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.


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