The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Dec. 21, 2012
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Chih-Yang Chang, San Jose, CA (US);

Sean S. Kang, San Ramon, CA (US);

Chia-Ling Kao, San Jose, CA (US);

Nikolaos Bekiaris, Los Altos, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C03C 15/00 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01L 21/3105 (2013.01); H01L 21/31116 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76814 (2013.01);
Abstract

Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF, H, and a diluent inert gas composition.


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