The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Nov. 15, 2013
Applicant:

Uniquify, Incorporated, San Jose, CA (US);

Inventors:

Jung Lee, San Jose, CA (US);

Mahesh Goplan, Santa Clara, CA (US);

Assignee:

Uniquify, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/12 (2006.01); G06F 1/04 (2006.01); H03K 19/173 (2006.01); H03K 19/00 (2006.01); G11C 11/00 (2006.01); G11C 8/16 (2006.01); G01R 35/00 (2006.01); G01R 27/28 (2006.01); G06F 12/00 (2006.01); G11C 29/00 (2006.01); G01R 31/28 (2006.01); G06F 1/08 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G06F 12/06 (2006.01); G11C 7/22 (2006.01); G06F 3/06 (2006.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 29/02 (2013.01); G11C 29/028 (2013.01); G11C 29/50 (2013.01); G11C 29/50012 (2013.01); G06F 1/12 (2013.01); G06F 12/0646 (2013.01); G11C 7/222 (2013.01); G06F 1/04 (2013.01); G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 1/14 (2013.01);
Abstract

A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.


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