The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Dec. 06, 2012
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Sheng Chang, Hangzhou, CN;

Rongyu Yang, Hangzhou, CN;

Xinyu Hou, Hangzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 15/17 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/40 (2013.01); G06F 13/4265 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0038 (2013.01); G06F 2213/3852 (2013.01); G06F 15/17 (2013.01); G06F 13/4059 (2013.01);
Abstract

The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.


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