The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Nov. 14, 2006
Applicants:

Partha Sriram, Los Altos, CA (US);

Robert Quan, San Francisco, CA (US);

Bhagawan Reddy Gnanapa, Andrha Pradesh, IN;

Ahmet Karakas, Palo Alto, CA (US);

Inventors:

Partha Sriram, Los Altos, CA (US);

Robert Quan, San Francisco, CA (US);

Bhagawan Reddy Gnanapa, Andrha Pradesh, IN;

Ahmet Karakas, Palo Alto, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/14 (2006.01); G06F 7/52 (2006.01); G10L 19/02 (2013.01); G10L 25/27 (2013.01);
U.S. Cl.
CPC ...
G06F 17/147 (2013.01); G10L 19/0212 (2013.01); G10L 25/27 (2013.01);
Abstract

In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.


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