The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Mar. 30, 2010
Applicants:

Maraki Maetani, Kyoto, JP;

Masahiko Hirose, Kyoto, JP;

Inventors:

Maraki Maetani, Kyoto, JP;

Masahiko Hirose, Kyoto, JP;

Assignee:

Kyocera Corporation, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); G02B 6/43 (2006.01); H01S 5/022 (2006.01); H01S 5/183 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
G02B 6/43 (2013.01); H01S 5/02292 (2013.01); H01S 5/183 (2013.01); H05K 1/0245 (2013.01); H05K 1/0274 (2013.01); H05K 3/4644 (2013.01); H05K 2201/09672 (2013.01); H05K 2201/09972 (2013.01);
Abstract

The invention relates to an optical-electrical wiring board () and an optical module (). The optical-electrical wiring board () includes a substrate (), a dielectric layer (), first conductive layers () and second conductive layers (). The dielectric layer () includes a first region (B) and a second region (C). The first region (B) constitutes a plurality of light transmission portions (B). The second region (C) has a plurality of pairs of conductive layers each having an overlap portion () in which one of the plurality of second conductive layers () and one of the plurality of first conductive layers () overlap each other when seen through in a laminated direction (a) of the dielectric layer () and the substrate ().


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