The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Feb. 19, 2013
Applicants:

Avinash Gutta, Pondicherry, IN;

Alan Gillespie, East Lothian, GB;

Roderick Mclachlan, Edinburgh, GB;

Inventors:

Avinash Gutta, Pondicherry, IN;

Alan Gillespie, East Lothian, GB;

Roderick McLachlan, Edinburgh, GB;

Assignee:

Analog Devices Global, Hamilton, BM;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03K 3/356 (2006.01); H03M 1/66 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356139 (2013.01); H03M 1/66 (2013.01); H03K 17/00 (2013.01);
Abstract

A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.


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