The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2015
Filed:
Apr. 06, 2012
Donald A. Hitko, Grover Beach, CA (US);
Carson R. White, Agoura Hills, CA (US);
Michael W. Yung, Los Angeles, CA (US);
David S. Matthews, Oxnard, CA (US);
Susan L. Morton, Pittsford, NY (US);
Jason W. May, Santa Monica, CA (US);
Joseph S. Colburn, Malibu, CA (US);
Donald A. Hitko, Grover Beach, CA (US);
Carson R. White, Agoura Hills, CA (US);
Michael W. Yung, Los Angeles, CA (US);
David S. Matthews, Oxnard, CA (US);
Susan L. Morton, Pittsford, NY (US);
Jason W. May, Santa Monica, CA (US);
Joseph S. Colburn, Malibu, CA (US);
HRL Laboratories, LLC, Malibu, CA (US);
Abstract
A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as 'non-Foster circuits.' The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).