The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2015
Filed:
Jan. 31, 2011
Applicants:
Jeff Rysinski, Pasadena, CA (US);
Yibing Michelle Wang, Temple City, CA (US);
Sang-soo Lee, Cupertino, CA (US);
Inventors:
Jeff Rysinski, Pasadena, CA (US);
Yibing Michelle Wang, Temple City, CA (US);
Sang-Soo Lee, Cupertino, CA (US);
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/02 (2006.01); H03F 3/45 (2006.01); H03K 5/24 (2006.01); H03M 1/12 (2006.01); H03M 1/56 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45188 (2013.01); H03K 5/2481 (2013.01); H03M 1/123 (2013.01); H03M 1/56 (2013.01); H03F 2203/45292 (2013.01); H03F 2203/45302 (2013.01); H03F 2203/45674 (2013.01);
Abstract
Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.