The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Feb. 20, 2013
Applicant:

Renesas Electronics Corporation, Nakahara-ku, Kawasaki-shi, Kanagawa, JP;

Inventor:

Yukio Maki, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/105 (2006.01); H01L 27/11 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H01L 27/105 (2013.01); H01L 27/1108 (2013.01); H01L 27/1116 (2013.01); H01L 28/90 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer.


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