The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Jan. 12, 2011
Applicants:

Bernd E. Kastenmeier, Austin, TX (US);

Raman E. Evazians, Pflugerville, TX (US);

Inventors:

Bernd E. Kastenmeier, Austin, TX (US);

Raman E. Evazians, Pflugerville, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/76802 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A device structure includes an inter-level dielectric, a via, a first conductive trench, and a second conductive trench. The inter-level dielectric has a top surface and a bottom surface. The via extends from the top surface to the bottom surface. The first conductive trench extends from the top surface to a first depth below the top surface. The second conductive trench extends from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth.


Find Patent Forward Citations

Kastenmeier, Bernd. (2015). Methods of forming semiconductor devices having conductors with different dimensions (U.S. Patent No. 8987862). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8987862

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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