The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Jan. 31, 2014
Applicants:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Hitachi Ulsi Systems Co., Ltd., Kodaira-shi, Tokyo, JP;

Inventors:

Hiroshi Inagawa, Maebashi, JP;

Nobuo Machida, Takasaki, JP;

Kentaro Ooishi, Takasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/266 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 27/0629 (2013.01); H01L 29/4236 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7804 (2013.01); H01L 29/7808 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 27/088 (2013.01); H01L 21/266 (2013.01); H01L 27/0255 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/4232 (2013.01); H01L 29/4238 (2013.01);
Abstract

A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.


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