The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2015
Filed:
May. 15, 2014
Miaolin Tan, Suzhou, CN;
Zhihong Cheng, Suzhou, CN;
Juan Fu, Suzhou, CN;
Peidong Wang, Suzhou, CN;
Yali Wang, Suzhou, CN;
Miaolin Tan, Suzhou, CN;
Zhihong Cheng, Suzhou, CN;
Juan Fu, Suzhou, CN;
Peidong Wang, Suzhou, CN;
Yali Wang, Suzhou, CN;
Freescale Semiconductor, Inc, Austin, TX (US);
Abstract
A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.