The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Feb. 06, 2014
Applicants:

Takahiro Koyama, Tokyo, JP;

Sadayuki Okuma, Tokyo, JP;

Inventors:

Takahiro Koyama, Tokyo, JP;

Sadayuki Okuma, Tokyo, JP;

Assignee:

PS4 Luxco S.A.R.L., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); G01R 31/26 (2014.01); G11C 29/12 (2006.01); G11C 29/26 (2006.01); G11C 29/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2644 (2013.01); G11C 29/1201 (2013.01); G11C 29/26 (2013.01); G11C 29/48 (2013.01); H01L 24/49 (2013.01); G11C 2029/2602 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/4824 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01055 (2013.01); H01L 2924/014 (2013.01);
Abstract

A semiconductor device includes at least two semiconductor chips each including a plurality of data input/output pads, a data memory portion structured so as to read/write data through the plurality of data input/output pads, a test result input/output pad, and a test circuit for controlling a first test mode that decides data read from the data memory portion and outputs the decision from the test result input/output pad and a second test mode that decides data read from the data memory portion, inputs test result of another semiconductor chip from the test result input/output pad and outputs a synthesized test result of the test result of the chip itself and the test result of the other semiconductor chip from a specified part of the plurality of data input/output pads, and a plurality of data input/output terminals each connected with different data input/output pads.


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