The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Oct. 21, 2011
Applicants:

LI Zhang, Jiangsu, CN;

Zhiming Lai, Jiangsu, CN;

Dong Chen, Jiangsu, CN;

Jinhui Chen, Jiangsu, CN;

Inventors:

Li Zhang, Jiangsu, CN;

Zhiming Lai, Jiangsu, CN;

Dong Chen, Jiangsu, CN;

Jinhui Chen, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49582 (2013.01); H01L 23/3107 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/95 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/03334 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0382 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01);
Abstract

Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (-) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (-) onto the carrier wafer for packaging; bonding a support wafer (-) onto the thin film layer I (-) and solidifying; forming a reconstructed wafer consisting of the chip (-), thin film layer I (-), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (-) on thin film layer I (-); forming a metal column (-) at an end of the rewired metal wiring (-); attaching thin film layer II (-) onto a surface of the metal column (-), packaging, and solidifying; coating a metal layer (-) on the top of the metal column (-), forming BGA solder balls (-) on the metal layer (-) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (-).


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