The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Oct. 29, 2010
Applicants:

Dick Scholten, Stuttgart, DE;

Michael Stumber, Korntal-Muenchingen, DE;

Franz Laermer, Weil der Stadt, DE;

Ando Feyh, Palo Alto, CA (US);

Inventors:

Dick Scholten, Stuttgart, DE;

Michael Stumber, Korntal-Muenchingen, DE;

Franz Laermer, Weil der Stadt, DE;

Ando Feyh, Palo Alto, CA (US);

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A61M 5/00 (2006.01); A61M 37/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
A61M 37/0015 (2013.01); B81C 1/00111 (2013.01); A61M 2037/0053 (2013.01); B81B 2201/055 (2013.01); B81B 2203/0361 (2013.01); B81C 2201/0114 (2013.01); B81C 2201/0115 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/054 (2013.01);
Abstract

A manufacturing method for a porous microneedle array includes: forming a plurality of porous microneedle arrays, each having at least one microneedle and a porous carrier zone lying beneath it on the face of a semiconductor substrate; forming an interlayer between a non-porous residual layer of the semiconductor substrate located on the back side of the semiconductor substrate and the carrier zone, which has greater porosity than the carrier zone; detaching the residual layer from the carrier zone by breaking up the interlayer; and separating the microneedle arrays into corresponding chips.


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